Microsoft Cloud Authors: Jim Kaskade, Lori MacVittie, Janakiram MSV, Andreas Grabner, Pat Romanski

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Real Intent Unveils Major Performance Enhancements in Ascent IIV and Ascent XV Tools for Early Functional Verification of Digital Designs

SUNNYVALE, CA --(Marketwire - January 30, 2013) - Real Intent, Inc., a leading provider of EDA software products today announced new releases of its Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools for early functional analysis of digital designs, delivering significant performance enhancements for users. Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved quality of results (QoR) and productivity of design teams.

Among new Ascent IIV features and enhancements are:

  • Up to 50-percent faster performance on designs greater than 100K gates
  • Incremental runs enabling users to resume previous analysis and avoid a complete re-start
  • A new double-toggle net check that eliminates toggle net false positives caused by reset state values
  • VCD traces that provide a marker to show the time of failure.

Likewise, new features in Ascent XV for detecting unknowns in digital hardware include:

  • Enhanced modeling of X's that come from retention flops, a major source of X's in a design
  • Broader coverage in identifying all X-sources and X-sensitive logic found by fast design audit
  • Tighter SimPortal integration to logic simulation that automatically generates a simulation free of unnecessary X issues
  • A new debug interface that shows the path from the sensitive construct to an X-source, facilitates waivers of X-sources and X-sensitive nets, and provides links for source code navigation

Lisa Piper, technical marketing manager at Real Intent, said, "The enhanced performance of IIV means designers can find more bugs more quickly without the need for any test benches. And our latest release of XV provides a unique X-hazard report that quickly pinpoints where sources of unknowns can obscure functional bugs or generate false problems in gate-level netlists. IIV's 50-percent faster performance for blocks greater than 100K gates and XV's enhanced detection of unknowns (X's) in digital hardware including retention flops are further proof that Real Intent delivers what we believe are the industry's best-in-class tools. Our Ascent products are the fastest and highest-capacity verification solutions available for uncovering issues prior to digital simulation."

Enhanced Debug and Language Support

Ascent IIV and Ascent XV now deliver enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. They also come with Verdi3 integration now to support this industry-leading debug platform from Synopsys (formerly SpringSoft).


The latest releases of Ascent IIV and Ascent XV are available immediately for download from the Real Intent web-site.

About Ascent IIV

Ascent IIV is a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. No test bench is needed, making it easy and efficient to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis minimizes debug time by identifying the root cause of issues and provides the VCD traces that show the sequence of events that lead to an undesired state. Ascent IIV has the speed and capacity to handle design blocks exceeding 100K gates and provides a wide variety of complex checks including FSM deadlocks, bus issues and constant bits and nets. If SystemVerilog Assertions (SVA) or VHDL assertions written in Property Specification Language (PSL) are available, Ascent IIV can use these as constraints to enhance the analysis. To see a video interview about Ascent IIV by Chris Morrison, chief architect at Real Intent, please visit: http://www.youtube.com/watch?v=i1fWKsdRcAQ

About Ascent XV

Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X's caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level. To see a video interview about Ascent XV by Lisa Piper, please visit: http://www.youtube.com/watch?v=ya7HPfm1bsU.

About Real Intent

Companies worldwide rely on Real Intent's EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent's Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.

CDC:      Clock Domain Crossing                            
EDA:      Electronic Design Automation                     
FSM:      Finite-State Machine                             
GUI:      Graphical User Interface                         
IEEE:     Institute of Electrical and Electronics Engineers
RTL:      Register Transfer Level                          
SoC:      Systems-on-Chip                                  
VCD:      Value Change Dump                                
VHDL:     Very High-level Design Language                  

Ascent and Meridian are trademarks of Real Intent, Inc.

All other trademarks and trade names are the property of their respective owners.

Image Available: http://www.marketwire.com/library/MwGo/2013/1/29/11G003528/Images/Ascent-1edc79f4-da3a-4be7-9ad0-154c1eb9ba00.jpg

Embedded Video Available: http://www.youtube.com/watch?v=ya7HPfm1bsU
Embedded Video Available: http://www.youtube.com/watch?v=i1fWKsdRcAQ

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